1. Field
Exemplary embodiments of the present invention relate to semiconductor design and more particularly, to a semiconductor memory device for storing data.
2. Description of the Related Art
Semiconductor memory devices are classified into volatile memory devices, such as a Dynamic Random Access Memory (DRAM) device and a Static RAM (SRAM) device, and non-volatile memory devices, such as a Programmable Read Only Memory (PROM) device, an Erasable PROM (EPROM) device, an Electrically EPROM (EEPROM) device, and a flash memory device. The main difference between the volatile memory devices and the non-volatile memory devices is whether the devices retain data when power supply is cut off. In other words, the volatile memory devices lose the data stored therein when power is turned off, while the non-volatile memory devices retain the data stored therein even though power is turned off. Therefore the volatile memory devices require an additional circuit to retain the data stored therein.
The non-volatile memory devices may have better characteristics than the volatile memory devices in terms of retainability of data. However, the volatile memory devices are superior to the non-volatile memory devices in terms of size and speed of the device circuits for the same storage capacity. Therefore, the volatile memory devices or the non-volatile memory devices are selected according to the purpose of a memory system. In short, the volatile memory devices are included in a memory system that mainly requires good access speed and the non-volatile memory devices are included in a memory system that mainly requires retainability of data.
Meanwhile, a flash memory device of the non-volatile memory devices stores a data in a memory cell through a programming operation and an erasing operation. The programming operation is an operation of accumulating electrons in a floating gate of a transistor that constitutes a memory cell, and the erasing operation is an operation of discharging the electrons accumulated in the floating gate of the transistor into a substrate. The flash memory device stores a data of ‘0’ or ‘1’ in a memory cell through the operations, and during a reading operation, it senses the amount of electrons accumulated in the floating gate and decides whether the data stored in the memory cell is ‘0’ or ‘1’ based on the sensing result.
One memory cell stores one bit data and this kind of memory cell is referred to as a single level cell. In these days, however, the flash memory device stores a data of more than one bit in one memory cell, which is referred to as a multi-level cell. In the case of the single level cell, one decision voltage, which is called a single threshold voltage, is required in order to decide whether the data stored in the memory cell is ‘0’ or ‘1’. In the case of the multi-level cell, at least three threshold voltages are required in order to decide whether the data stored in the memory cell is ‘00’, ‘01’, 10’ or ‘11’.
Data stored in the flash memory device have a data distribution according to a value of the data. The data distribution, however, may overlap with an adjacent data distribution and due to the overlap between the neighboring data distributions, there may occur a read error that the data decided based on the threshold voltage and the data substantially stored in the memory cell during a reading operation. Recent progress in fabrication and design makes data distributions narrower but it also makes margin between the neighboring data distributions narrower as well, which means that the overlap between the neighboring data distributions becomes greater, and thus the probability of the read error becomes higher.
N-bit over-sampling emerges lately to prevent the error. According to the n-bit over-sampling, (2n)−1 threshold voltages are used to distinguish different data distributions from each other instead of one threshold voltage.
FIGS. 1 and 2 are data distribution diagrams illustrating the n-bit over-sampling.
FIG. 1 shows a 1-bit over-sampling (A), a 2-bit over-sampling (B), and a 3-bit over-sampling (C). Referring to FIG. 1, the 1-bit over-sampling (A) uses one threshold voltage, and the 2-bit over-sampling (B) uses three threshold voltages. The 3-bit over-sampling (C) uses seven threshold voltages. Since a reading operation has to be performed for each threshold voltage, the reading operation is performed seven times in the case of the 3-bit over-sampling (C).
FIG. 2 exemplarily shows the 3-bit over-sampling being applied to a multi-level cell where a two-bit data is stored in one memory cell.
Referring to FIG. 2, in the case of the multi-level cell that stores a two-bit data, the Most Significant Bit (MSB) and the Least Significant Bit (LSB) have to be decided during the reading operation. Since each of the MSB and the LSB has to be over-sampled at seven threshold voltages, the reading operation has to be performed in a total of 21 times (21=3*{(23)−1}).
If a 4-bit over-sampling is applied to a multi-level cell where a two-bit data is stored in one memory cell, the reading operation has to be performed in a total of 45 times (45=3*{(24)−1}). Assumed that it takes approximately 20 μs to perform the reading operation once, it takes approximately 420 μs to read the data stored in the memory cell in the case of the 3-bit over-sampling and approximately 900 μs in the case of the 4-bit over-sampling.
As the number of bits to be over-sampled increases, it takes longer time to perform a reading operation on one memory cell.